Pepino, meet Oberon. Oberon, meet Pepino.
Pepino is designed from the ground up to run the Oberon RISC system as described in Project Oberon (New Edition 2013).
For more info about Project Oberon see www.projectoberon.com
The board is shipped with Oberon RISC bitfile installed in flash and is ready to boot from an sd-card with an Oberon image (sd-card not included but available in the store: microSD card).
You need the following parts to set up a fully functioning Oberon workstation:
- VGA monitor capable of displaying 1024x768 @ 60Hz
- PS/2 Keyboard
- PS/2 Mouse (three button or with scrollwheel button)
- micro SD-card with Oberon image installed (available here.)
- mini-USB cable
- USB power supply or PC with USB port
- (optional) nRF24L01+ wireless module for networking (available here.)
A suitable Oberon image can be downloaded from ProjectOberon:RISCimg.zip.
You need to un-zip the file and write the raw file system image to the sd-card using an image raw-writing program like dd (unix/linux/mac) or win32diskimager (windows). (Note: you can not simply copy the image file to the sd-card.) Writing the image file will erase all data on the sd-card!
Unix/Linux/OSX: (as root or prepend with sudo)
umount /dev/<your sd device>
dd if=RISC.img of=/dev/<your sd device>
Launch Win32DiskImager, select RISC.img as the Image File, select your sd-card as the Device and click Write
Modifications from the Digilent Spartan3 code base
The Pepino version is based on the "10/27/2015" RISC5Verilog release with only a handfull of lines changed. The changes are related to the instantiation of the DCM, the changes to the VGA interface (8-bit video vs. 3-bit video), and the addition of an sd-card activity LED. The Pepino version (including both the original and modified code as well as ISE project files for Pepino_LX9 and Pepino_LX25 and bit files for both boards) can be downloaded from here: RISC5Verilog_Pepino.zip or from the Pepino GitHub repository: Pepino Projects
The board has two expansion connectors, J7 and J8. The tables below shows the pinout of the connectors when holding the board with the VGA connector facing up:
Connector J7 has (in addition to power and ground) 6 signals directly connected to the FPGA. The connector is wired to accept the nRF24L01+ RF module used for networking in Oberon, with the signals mapped as follows (IRQ not used by the Oberon code).
See this link for more info about nRF24L01+.
Connector J8 has (in addition to power and ground) 16 signals directly connected to the FPGA. In the Oberon code the 16 signals are mapped to the 8-bit GPIO bus and the four BTN signals.
The BTN signals have pulldown enabled and should be pulled to 3.3V in order for the Oberon code to read it as high.
DIP-switch and LEDs
The board has 8 DIP switches and 8 LEDs
The DIP switches are mapped in the Oberon code as follows:
The LEDs are mapped in the Oberon code as follows: