Pepino as Logic Analyzer
The Open Bench Logic Sniffer code has been ported to Pepino. For more info about Pepino see the Pepino page
This code is based on the original SUMP logic analyzer project, with capture memory increased from 24KB to 1MB while retaining most functions of the Open Bench Logic Sniffer.
Modifications from the Open Bench Logic Sniffer code base
The Open Bench Logic Sniffer code has been updated with the following additions/modifications:
- Max 16 channels available (max 8 channels in 200 MHz capture mode)
- The sample memory is increased from 24 KB to 1 MB using the on-board SRAM memory
- The ability to trigger on rising/falling edges in addition to high/low levels
- Extensions to the SUMP protocol to increase the maximum sample count (the original SUMP protocol limits the sample count to 256K samples)
- Increased I/O data rate (from 115200 to 921600 baud)
I/O Buffer board
The I/O pins on the Pepino board can only be used with logic levels up to 3.3V. To support 5V logic there is an add-on board that has a 5V tolerant input buffer.
See this page for info about the buffer board.
It's strongly suggested that the buffer wing is used to protect the Pepino board input pins.
Bit files and source code
Bit files (all versions) are available here: Pepino_OLS_bitfiles.zip.
Verilog source code and Xilinx ISE project files are available here: Pepino_OLS.zip
Modified version of JaWi's SUMP client with Pepino support available here: ols-0.9.7.2-pepino.zip
How to use with JaWi's SUMP client
See above for a link to a modified version of JaWi's SUMP client with added support for Pepino.
It can also be used with the official release of the JaWi SUMP client with the following limitations:
- Maximum sample count is 256K samples
- Edge triggers are not supported
- Channel groups 2 and 3 should not be enabled
- Channel group 1 should not be enabled in 200 MHz sampling rate
Steps to get it up and running:
1) Connect the Pepino board to the computer
2) Load or flash the bitfile to Pepino.
3) Start JaWi's SUMP client
4) Under the "Capture" pulldown menu, select "Begin capture". This will bring up the configuration menus
5) In the "Connection" tab:
- set Connection type to Serial port
- set Analyser port to the Pepino COM port
- set Port Speed to 921600bps
6) To verify the connection press "Show device metadata" which should report that it found Pepino OLS 1MB
Use the following steps to capture some data:
7) In the "Acquisition" tab
- set Number scheme to Inside
- set Sampling clock to Internal
- set Sampling rate to 100 MHz
- enable Channel groups 0 and 1
- set Recording Size to 128.00 kB
- enable Test mode (this will configure ch8 - ch15 as outputs and driven with a test sequence)
- disable Noise filter
- disable Run Length Encoding
8) In the "Triggers" tab
- enable Trigger
- set Before/After ratio to 10/90
- set Type to SIMPLE
- set Mask, Value and Edge for ch 15 (trigger on rising edge on ch 15)
9) Press Capture
You should see the test sequence on ch 8 - 15 (just a binary counter).
See this link for info about the original SUMP logic analyser project written in VHDL.
See this link for info about Open Bench Logic Sniffer (derived from SUMP, ported to Verilog).
See this link for information about JaWi's Java-based SUMP client that runs on the PC.